CSMA/ECA, Channel errors, Schedule Reset and NS-3

In this attempt we implemented some kind of channel-induced errors.

Ok, I know, it is not that specific, but the thing is that there are situations in which the Ack Timeout is reached, and most of the time it is because a frame was corrupted.

Instead of assigning a Bit Error Rate (BER), we defined a Frame Error Rate (FER) that works over the whole AMSDU. That is, if the received PLCP is affected negatively by the FER, then the whole AMSDU will be discarded.

The following are results of a saturated IEEE 802.11n network working with Mcs 7, a single 20 MHz channel and FER = 10%.


Fig. 1 Throughput

Fig. 1 Throughput

As expected, aggregation via Fair Share ensures greater throughput. Furthermore, we can see the effects of the Schedule Reset Mechanism, which shows greater throughput for the CSMA/ECA+Hyst SH dynStick curve than for the CSMA/ECA+Hyst test. The latter having very low throughput due to nodes reaching the maximum deterministic backoff very quickly.

Another interesting observation can be made about the dynStick-1 curve (default stickiness = 1, so the increase after a successful schedule reduction will render succ_stickiness = 2). As this setup prevents the Wifi nodes’ deterministic backoff from getting to big, the level of aggregation is also reduced.


Failed transmissions

Fig. 2 Failed Transmissions

Fig. 2 Failed Transmissions

Even though FER=10%, the dynStick-1 curve shows lower losses for less than 8 Wifi nodes. This is because the default level of stickiness prevents increases in the losses counter. If instead we count the reduction from stickiness = 1 to 0 as a lost frame, FER-induced losses will level the curve much more like CSMA/ECA+Hyst’s.


Time between successful transmissions

Fig. 3 Time Between Sx Tx

Fig. 3 Time Between Sx Tx

We can see how aggregation increases the time between successful transmissions. Moreover, the big deterministic backoff selected by CSMA/ECA+Hyst nodes also increases the time between successful transmissions (all the nodes end-up with the highest deterministic backoff possible, which is CWmax/2 = 512).

As SH dynStick-1 prevents the deterministic backoff from getting to large, less aggregation is performed and the time between successful transmissions is also reduced.


Jain’s Fairness Index (JFI)

Fig. 4 Fairness

Fig. 4 Fairness

There is no surprise that CSMA/ECA+Hyst SH dynStick is quite unfair. The schedule reduction will force some nodes to have shorter cycles than others, and this issue is not leveraged with Fair Share, as opposed to CSMA/ECA+Hyst+FS SH dynStick.

We can also see that CSMA/ECA+Hyst appears to have a JFI = 1. This is because the FER forces the nodes to the highest deterministic backoff very quickly.


NOTE: during our real hardware implementation we tested CSMA/ECA+Hyst SH dynStick-1.


Posted under: CSMA/ECA, Fair Share, Hysteresis, MAC, NS3, WiFi

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